MOS (metal oxide semiconductor) transistor technology was developed and became practical few decades ago, several types of memory devices were introduced since that time among them are UVEPROMs, full-featured EEPROMs, Flash-EEPROMs, Analog Storage EEPROMs, volatile DRAMs, non-volatile DRAMs, volatile SRAMs, non-volatile SRAMs, Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), Artificial Neural Network (ANN) devices, and other customized memory devices.
Volatile SRAM is a static read/write random access memory whose storage cells are remain in a given state until the information is intentionally changed, or the power to the memory circuit is cut off.
Volatile dynamic random access memories (DRAMs) is likewise a semiconductor memory that stores binary information. The word "dynamic" refers to the fact that the charge representing the stored information is refreshed or replenished. Typically the information stored in the capacitor of each memory cell is either a "1" or a "0" representing one digital bit per one physical memory cell. Later this data may be read out from the memory cell of the device. The most commonly used DRAM chip is a read/write random access memory which is based on a memory cell that is structures to include one transistor one capacitor combination, in which the digital information is represented by charges that are stored in the storage capacitor. The storage capacitor has one of its plates acting as a storage node and the other plate acting as a plate that is connected to adjacent memory cell capacitors and is biased at some voltage. When the memory cell is not-selected (also referred to below as deselected) the memory cell transistor is turned off and disconnects the storage plate of the capacitor from any voltage or current source and the storage plate of the DRAM's capacitor is said to be floating.
In a dynamic random access memory or DRAM the information is refreshed or rewritten as needed to avoid losing information because of electrical activity and read/write operations in the memory array including operations associated with neighboring memory cells. In this way a high or "1" logical level signal is restored to a stored "1." The refresh operation occurs by sensing or reading what is stored in a memory cell and restoring it to the proper voltage level that represents the same logical state.
There have been significant advances in the art of memory cells. Many such advances are equally applicable to both EEPROMS and DRAMs, and it should be understood that new or improved element of a cell structure can be of great utility in any semiconductor memory cell. The utility is more noticeable when the memory cell is comprised of fewer elements. For example a DRAM memory cell (either volatile or non-volatile) having a transistor and a capacitor typically uses a MOSFET transistor and a capacitor structure of the same materials that are used in some EEPROMs such as the EEPROMs disclosed in U.S. Pat. Nos. 4,845,538 and 5,166,904 issued to the applicant of this application and are expressly incorporated herein by reference.
Non-Volatile SRAMs (NOVRAMs) were developed in the early 1980's and include a cell that is comprised of a combination of SRAM cell element and at least a portion of an EEPROM cell element.
Generally the goal in forming any memory device is to minimize the physical size of the memory cell and memory array thereby to maximize the packing density of cells per chip area which results in exponential increase in the production yield of good chips from a semiconductor wafer.
Generally, it is desirable to have the highest value of charge possible stores in the memory cell capacitor, especially since the memory cells are getting smaller in each new generation of DRAMs and EEPROMs. Storing higher value of charge in the capacitor generally leads to more reliable operation, higher immunity to soft errors caused by alpha-particles and higher speed operation due to the improved ratio of cell signal to array noise. To increase the amount of stored charge in the memory cell, either the voltage or the capacitance, or both, must be increased according to the charge equation Q=CV, where Q is the charge value, C is the capacitance value and V is the voltage value. Certain tradeoffs are involved in the method selected to increase the stored charge. If one decides to increase the capacitance of the memory cell, either a larger physical capacitor footprint area is needed which exponentially increases manufacturing cost of the memory chip, or some innovative solution is required (such as disclosed and claimed by the Applicant of the instant application in U.S. Pat. No. 5,166,904) in order to reduce the physical footprint area of the storage node of the capacitor using economically affordable semiconductor chip fabrication processing steps. On the other hand, increasing the voltage on the chip is not desired because it increases the programming time in of the cells in EEPROMs, causes reliability constrains which prevents the use of thin dielectric layers within the memory cell capacitor and under interconnect lines that form the memory array and its associated peripheral circuits and reduces efficiency. It would be greatly advantageous to provide a memory cell with increased capacitance and reduced operating voltages inside the chip.
U.S. Pat. No. 4,763,299 issued to the applicant herein programs by using hot electrons from the substrate. It has a very high programming efficiency. The programming time of a single cell of this embodiment is much shorter than that of a tunneling-program mechanism alone, in the range of one micro second (1 uS). This programming efficiency also reduces the programming drain-source current to about one microampere (1 uA), which is much lower in comparison to other cells that program by use of hot electrons from the substrate. The shorter programming time of the cell of '299 patent together with the low programming current becomes extremely advantageous in applications such as Solid-State-Disks for computers, hand-held computers, and for IC-Card Cameras in which the digitally processed image is rapidly stored in a EEPROM semiconductor memory which can be produce at lower cost than SRAM memory. It is estimated that the IC-Card Camera will take over the multi-billion dollar photographic market place in the near future. Construction of IC-Cards from memories that are based on chips that are constructed using memory cells that comprise one capacitor-one transistor configuration are much more suitable for use in IC-Cards because of the lower cost afforded by these type of memories as oppose to SRAM based IC-Cards.
It is desired to further reduce the programming/erasure voltage of EEPROM cells, while compensating by increasing the capacitance of the cells, while reducing the cell size in order to reduce production cost. Preferably, the foregoing should be accomplished using conventional photolithography equipment (such as photo-light based step-and-repeat cameras and projection aligners, conventional chemicals and photoresists, etc.)
The memory array of memory chips can be further reduced in size if the arrangements of the memory cells, or groups of memory cells is configured in a novel way and in order to take advantage of certain constrains induced by characteristics of materials and known practical limitations of processing equipment for forming structures such as interconnect wires from those materials. For example it is known that a common interconnect metal in chips is formed of aluminum-silicon-copper, which has a low ohmic sheet resistance per square of below 40 milliohm, however the definition of a minimum line width of interconnect is typically much wider than the line width of polycrystalline silicon interconnect which has ohmic sheet resistance per square of about 30 ohms. This brings about the need to take advantage of this facts in order to further reduce the size of the memory array matrix beyond the size reduction that is contributed by the advantage of the memory cell.
The storage density of information in a memory chip can also be increased beyond the contribution of the advantages of the physical memory cell by storing more than one logical bit per physical memory cell. This is disclosed in some details in U.S. Pat. No. 5,278,785 issued to the applicant of this application and which is incorporated herein by reference. Memory chips or memory systems that use such a storage concept can benefit from improved reliability of the stored data within the physical memory cell and from improved performance of such memory cells.